Implementation of Power and Delay Efficient SRAM Design

SEEE DIGIBOOK ON ENGINEERING & TECHNOLOGY, VOL. 01, FEB 2018 PP.(247-251)

Abstract– Based on Recent studies in memory systems, peripheral circuits especially word line drivers constitute a large portion of the cache leakage. In addition as technology migrate to smaller geometries, leakage contribution to total power consumption increases faster than dynamic power, promoting leakage as the largest power consumption factor. In the past few years, numerous strategies have arisen for decreasing the chip size in SRAM. However, with technology scaling, it is becoming very difficult to maintain the better results for power reduction. In comparison with standard memory cells, the peripheral circuit dissipates excessive power. Power dissipation has become an important consideration for designing buffer because these circuits do not only amplify the signal but also drive the large capacitive loads with high driving speed. For many designs, optimization power is important for extended battery life of portable systems. The main objective of this paper is to reduce the power dissipation by exploiting CMOS taper buffer topology consisting of inverter stages which act as a word line drivers in SRAM design. The power and delay efficient SRAM have been designed using Cadence Virtuoso Analog design environment in 180nm technology.

Index Terms – CMOS taper buffer, leakage power, sources of Power dissipation, SRAM design.

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Kanimozhi G, Vasanthanayaki C
Government College of Technology,
Coimbatore, India
kanimozhi3395@gmail.com,
c.vasanthi@gct.ac.in

Implementation of Power and Delay Efficient SRAM Design

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